The present disclosure relates to semiconductor devices and manufacturing methods of the devices, and more particularly to semiconductor devices with a structure suited for stacked packaging by using through-vias and manufacturing methods of the devices.
Known are semiconductor devices formed by three-dimensionally stacking a plurality of semiconductor devices for higher integration and miniaturization of semiconductor products.
Also, in recent years, semiconductor devices including through-vias have been developed as a technique of three-dimensionally stacking a plurality semiconductor devices.
Japanese Patent No. 4011695 shows an example (first conventional example) of a manufacturing method of a semiconductor device including a through-via.
According to the method, first, a hole (non-through hole at this time) is formed in a silicon substrate (before forming an interconnect and after forming an element) covered by an insulating film, from an element formation surface (front surface) toward the opposite surface (back surface). Then, after forming an insulating film (via coating film) to cover a sidewall surface of a non-through hole, a metal film is buried in the hole which becomes a through-via. Next, the metal film is removed by chemical mechanical polishing (CMP) or etch-back until the insulating film on the substrate surface is exposed. This forms a via structure inside the hole. After that, a multilayer interconnect structure is formed on a silicon substrate to be electrically connected to the via structure inside the hole. Then, the silicon substrate is polished from the back surface, thereby exposing the via structure inside the hole to the back surface of the substrate to form a through-via.
Japanese Patent No. 4145301 shows another example (second conventional example) of a manufacturing method of a semiconductor device including a through-via.
According to this method, first, a silicon substrate including an element and a multilayer interconnect layer at an element formation surface (front surface) is thinned from the back surface. Then, a through hole is formed from the back surface of the silicon substrate to reach an electrode pad inside the multilayer interconnect layer at the front surface. Next, after forming an insulating film (via coating film) to cover the sidewall surface of the through hole, a metal film is buried in the through hole by electroplating to form a through-via.